OCEOS/oceos kernel/interrupt

OCEOS Interrupts

Introduction

SPARC

Interrupt handler code is written by the application developer. Normal practice is to keep interrupt handlers as short as possible, and to delegate processing to an appropriate task by placing a job on the ready queue. If this is done, to ensure a high priority job is started immediately, the scheduler needs to be called at the end of interrupt processing, i.e. at the end of the outermost nested interrupt if nesting is used.

SPARC Interrupts Introduction

Interrupting traps are controlled by the Processor Interrupt Level (PIL) field of the Processor Status Register (PSR) and by the Trap Enable (ET) field of the PSR.
The Trap Base Address (TBA) in the Trap Base register (TBR) must be set to the top 20 bits of the trap table address, which must be on a 4k boundary for MVT.

When the target hardware is configured to support single vector trapping (SVT), the -qsvt switch can be used with the linker to build an image which uses a two-level trap dispatch table rather than the standard one-level trap table. The code saving amounts to ~4KiB for the trap table and trap handling is slightly slower with single vector trapping. The number of extra instructions needed for single vector trapping dispatching is constant.

Interrupts are re-enabled automatically on exit from the interrupt handler, when the processor state is restored to its previous value. Alternatively, the interrupt handler itself can re-enable interrupts before processing of the current interrupt is complete. If this is done a higher priority interrupt can pre-empt the processor from the current interrupt handler and 'interrupt nesting' occur.

OCEOS can be configured to use interrupt nesting.

During OCEOS initialization, each IRQ handler entry in Vector table is replaced with OCEOS interrupt handler for Multi or Single Vector Table (MVT or SVT). User must call OCEOS directives for registering and unregistering IRQ handlers. If IRQ is asserted, then OCEOS service code runs first, then user code => to handle IRQ and then finishes OCEOS handler code. This way the scheduling is possible to perform and other necessary OCEOS system calls.

SPARC Interrupts Configurations

User must not modify Interrupt Vector Table directly. User must use OCEOS directive oceos_interrupt_handle_register() and oceos_interrupt_handle_unregister() to register/unregister Interrupt handlers.

Interrupt nesting is disabled by default in BCC, meaning that an interrupt service routine can not be preempted by any other interrupt.

/*
 * Create the application configuration structure
 */
 struct application_configuration           app_config = {0};
 app_config.interrupt_nesting_enabled     = FALSE;

Disable interrupt nesting in OCEOS. PSR.PIL will be raised to 0xf (highest) when an interrupt occurs on any level.

/*
 * Create the application configuration structure
 */
 struct application_configuration           app_config = {0};
 app_config.interrupt_nesting_enabled     = TRUE;

Enable interrupt nesting in OCEOS. PSR.PIL will be raised to the current interrupt level when an interrupt occurs.

Support for single vector trapping (SVT) in OCEOS is enabled when application developer passes -qsvt switch to BCC Linker

ARM Cortex-M

ARM Cortex-M Interrupts Introduction

ARM Cortex-M uses Nested Interrupt Controller. User must modify Vector Trap table to add IRQ handlers for required IRQs.

Note

OCEOS uses some Exception handlers for own needs. User must pay attention to such handlers and not replace :

• oceos_SysTick_Handler()
• oceos_PendSV_Handler()

ARM Cortex-M processor has two modes:

• Thread Mode
• Handler Mode

OCEOS is running in Thread mode. OCEOS uses only one stack (main stack). When task is started by IRQ handler (in Handler mode) OCEOS has to switch to Thread mode in order to schedule execution of the task. For this purpose, OCEOS uses PendSV exception and implements oceos_PendSV_Handler() which must be present in Vector table (user responsibility).

Note

OCEOS initializes PendSV exception to the lowest priority (0xFF) and no other exceptions must have the same priority (user responsibility).

When task is started in IRQ handler, OCEOS asserts PendSV exception and because it is the lowest priority, it serviced at the end when nesting level is zero.