Difference between revisions of "OCEOS/oceos kernel/timer"
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=<span style="color:#0000ff">'''OCEOS System Time'''</span>= | =<span style="color:#0000ff">'''OCEOS System Time'''</span>= | ||
==<span style="color:#0000ff">Introduction</span>== | ==<span style="color:#0000ff">Introduction</span>== | ||
=== SPARC === | === <span style="color:#0000ff">SPARC</span> === | ||
In OCEOS system time is based on two chained 32-bit timers. | In OCEOS system time is based on two chained 32-bit timers. | ||
| Line 14: | Line 14: | ||
The system time is reset to 0 by oceos_init() | The system time is reset to 0 by oceos_init() | ||
=== ARM Cortex-M === | === <span style="color:#0000ff">ARM Cortex-M</span> === | ||
[[Category:backup]] | [[Category:backup]] | ||
Revision as of 11:54, 16 March 2022
OCEOS System Time
Introduction
SPARC
In OCEOS system time is based on two chained 32-bit timers.
No interrupts are involved, the current system time is obtained by reading the two timer counter registers (in an atomic way) and then inverting the values since the timers count down.
The scaler associated with the timers is configured based on the system clock frequency to decrement the low order timer every microsecond. This decrements the high order timer when it rolls over, every 71.6 minutes approximately. The 64-bit time range is very long, over 584,000 years. The system time is reset to 0 by oceos_init()